Gray scale technology for fabrication was also disclosed in U.S. Pat. No. 5,310,623 (Gal '623), “Method for Fabricating Microlenses,” issued 10 May 1994, the entirety of which is herein incorporated by reference. In Gal '623, a designed configuration was formed as a replica, which in turn was formed on photoresist material that was used to produce a configuration in a substrate material. The methodology disclosed in Gal '623 involved ultraviolet illumination through a single pixel binary exposure mask, which was subdivided into many subpixels, which in turn was divided into gray scale resolution elements. A replica image was produced by exposing photoresist material to light (through a gray scale model) of a selected wavelength transmitted through openings in the exposure mask for a selected duration of time. The exposed photoresist material was then processed to produce a replica in the photoresist material. As discussed in Gal '623, the process involved removing an amount of unhardened material from a particular subpixel area following light exposure, which produced a replica of the design. The mask opening in each subpixel provided a grey scale resolution depending upon the number of resolution elements incorporated within the mask opening. The gradation of the gray scale resolution ranged from a very light gradation (where the size of the mask opening comprises only a few resolution elements) to a relatively dark gray scale gradation (when the size of the mask opening included the maximum number of gray scale resolution elements for minimum exposure). The replica produced was then used for producing the design in a substrate material by differential ion milling.
Gray scale technology used in conjunction with silicon structures was disclosed in an article by Christopher M Waits, et al., entitled “Investigation of gray-scale technology for large area 3D silicon MEMS structures,” J. Micromech. Microeng. 13 170-177 (2003), hereby incorporated by reference. Also disclosed was a discussion of minimum usable pixel size, maximum usable pitch size and the range of usable gray levels for developing 3-D large area silicon structures, together with the resolution of a projection lithography system and the spot size used to write a binary optical mask.